Method of fabricating semiconductor device and semiconductor fabricated by the same method

ABSTRACT

A method of fabricating a semiconductor device and a semiconductor device fabricated by the same method are disclosed. The method includes: depositing a silicon layer containing amorphous silicon on a substrate using any one of a plasma enhanced chemical vapor deposition (PECVD) method and a low pressure chemical vapor deposition (LPCVD) method; annealing the silicon layer in an H 2 O atmosphere at a certain temperature to form a polycrystalline silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; forming impurity regions in the polycrystalline silicon layer to define source and drain regions; and activating the impurity regions. Thus, it is possible to provide a semiconductor device, in which the substrate is prevented from being bent and polycrystalline silicon constituting a semiconductor layer is excellent.

This application claims priority to and the benefit of Korean PatentApplication No. 2004-50863, filed Jun. 30, 2004, the contents of whichare hereby incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a semiconductordevice and, more particularly, to a method of fabricating asemiconductor device by which a substrate may be prevented from beingbent, and a semiconductor device fabricated by the same method.

2. Description of Related Art

Polycrystalline silicon is used in an active device for an organic lightemitting display device, normally, thin film transistors (TFTs), whichis used to supply current to pixel regions and peripheral drivingregions.

In general, the polycrystalline silicon is formed by crystallization ofamorphous silicon.

Normally, methods for the crystallization may be largely classified intoa low-temperature crystallization method and a high-temperaturecrystallization method depending on a crystallization temperature, forexample, with reference to about 500° C.

An excimer laser annealing (ELA) method using an excimer laser is mainlyused as the low-temperature crystallization method. The eximer laserannealing method may use a glass substrate since it is carried out at acrystallization temperature of about 450° C. However, manufacturing costis high and the substrate is constrained in an optimal size, therebyincreasing total cost to fabricate a display device.

The high-temperature crystallization method includes a solid phasecrystallization method, a rapid thermal annealing method, and the like.A low-cost annealing method is widely used as the high-temperaturecrystallization method.

However, since the solid phase crystallization method requires heatingat a temperature of more than 600° C. for 20 or more hours forcrystallization, many crystal defects are included in the crystallizedpolycrystalline silicon. Accordingly, sufficient electric field mobilitycannot be obtained, the substrate is prone to deform during an annealingprocess, i.e., a heat treatment process, and lowered crystallizationtemperature degrades productivity. Because the solid phasecrystallization method is also performed at high crystallizationtemperature, the glass substrate is not allowed to use.

Meanwhile, although the rapid thermal annealing (RTA) method may beaccomplished in relatively short time, the substrate is prone to deformdue to severe thermal shock and the crystallized polycrystalline siliconhas poor electrical characteristics.

Consequently, a low-cost high-temperature annealing method may berequired to be used upon the crystallization in order to reduce cost tofabricate the active device. Moreover, there is a need for ahigh-temperature annealing method using an inexpensive glass substrate,by which the glass substrate is not bent and crystallinity is excellent.

SUMMARY OF THE INVENTION

The present invention, therefore, solves aforementioned problemsassociated with conventional devices by providing a method offabricating a semiconductor device which is capable of crystallizingpolycrystalline silicon with excellent crystallinity and preventing asubstrate from being bent due to a high crystallization temperature uponcrystallization, and a semiconductor device fabricated by the samemethod.

In an exemplary embodiment of the present invention, a method offabricating a semiconductor device includes: depositing a silicon layercontaining amorphous silicon on a substrate using a plasma enhancedchemical vapor deposition (PECVD) method or a low pressure chemicalvapor deposition (LPCVD) method; annealing the silicon layer in an H₂Oatmosphere at a predetermined temperature to form a polycrystallinesilicon layer; forming a gate insulating layer on the polycrystallinesilicon layer; forming impurity regions in the polycrystalline siliconlayer; and activating the impurity regions.

In another exemplary embodiment of the present invention, a method offabricating a semiconductor device includes: depositing a silicon layercontaining amorphous silicon on a substrate using a plasma enhancedchemical vapor deposition (PECVD) method or a low pressure chemicalvapor deposition (LPCVD) method; doping the silicon layer with impurityions to define source and drain regions; patterning the amorphoussilicon to form a semiconductor layer; forming a gate insulating layeron the semiconductor layer over the substrate; forming a gate electrodeon the gate insulating layer, the gate electrode corresponding to achannel region of the semiconductor layer; and annealing the amorphoussilicon in an H₂O atmosphere at predetermined temperature to crystallizethe amorphous silicon and activate the impurity ions.

In yet another exemplary embodiment of the present invention, a methodof fabricating a semiconductor device includes: forming a gate electrodeon a substrate; forming a gate insulating layer on the gate electrodeover the substrate; depositing a silicon layer containing amorphoussilicon on the gate insulating layer using a plasma enhanced chemicalvapor deposition (PECVD) method or a low pressure chemical vapordeposition (LPCVD) method; doping impurity ions into the silicon layerusing photoresist to define source and drain regions; and removing thephotoresist and then annealing the amorphous silicon in an H₂Oatmosphere at a certain temperature to crystallize the amorphous siliconand to activate the impurity ions.

In still another exemplary embodiment of the present invention, asemiconductor device fabricated by the method, wherein the semiconductordevice is a thin film transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present invention will be describedin reference to certain exemplary embodiments thereof with reference tothe attached drawings in which:

FIGS. 1A to 1E sequentially illustrate a method of fabricating asemiconductor device according to a first embodiment of the presentinvention;

FIGS. 2A to 2E sequentially illustrate a method of fabricating asemiconductor device according to a second embodiment of the presentinvention;

FIGS. 3A to 3D sequentially illustrate a method of fabricating asemiconductor device according to a third embodiment of the presentinvention; and

FIG. 4 illustrates FWHM of a polycrystalline silicon thin filmfabricated by embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. In the drawings, the thickness of the layers andregions are exaggerated for clarity.

FIGS. 1A to 1E sequentially illustrate a method of fabricating asemiconductor device according to a first embodiment of the presentinvention.

Referring to FIG. 1A, amorphous silicon, or a silicon layer 12containing a great quantity of amorphous silicon is deposited on asubstrate 10. At this time, a normally used insulating and transparentglass substrate is used as the substrate 10.

A typical deposition method, such as a plasma enhanced chemical vapordeposition (PECVD) method or a low-pressure chemical vapor deposition(LPCVD) method, is used to deposit the silicon layer 12. The PECVDmethod is performed using SiH₄+Ar and/or H₂ under a pressure of 1 to 1.5Torr at a temperature of about 330 to about 430° C. Further, the LPCVDis performed using Si₂H₆+Ar under a pressure of 0.2 to 0.4 Torr at atemperature of about 400 to about 500° C.

Further, a buffer layer such as a silicon nitride (SiNx) layer or asilicon oxide (SiO₂) layer may be further formed on the substrate priorto depositing the amorphous silicon layer, in order to preventcontaminants or the like created in the substrate from diffusing intothe silicon layer or enhance interface characteristics between thesilicon layer and the substrate.

The amorphous silicon, or the silicon layer 12 that contains a greatquantity of amorphous silicon is then annealed, as shown in FIG. 1B. Atthis time, when the silicon layer is heated, the amorphous silicon ismelt. At the same time, the amorphous silicon is cooled and crystallizedinto the polycrystalline silicon. The polycrystalline silicon is thenpatterned to form a semiconductor layer 12 a.

In the present invention, a rapid thermal annealing (RTA) process or atypical high-temperature annealing process in a furnace is used as theannealing process. Conventional annealing is carried out in an inert N₂or O₂ atmosphere while the annealing in the present invention is carriedout in an H₂O atmosphere.

The annealing in the H₂O atmosphere shortens annealing time under acondition of the same temperature and reduces annealing temperatureunder a condition of the same time, compared to the annealing in the N₂or O₂ atmosphere.

In particular, a conventional glass substrate that is a transparentinsulting substrate is bent due to a high temperature while thesubstrate in the present invention is not bent because the annealingtemperature may be lowered.

In the present invention, the annealing temperature is preferably in therange of 550 to 750° C. More preferably, the annealing temperature is inthe range of 600 to 710° C. because excellent polycrystalline siliconmay be achieved with a proper annealing time. Crystallization may not beachieved when the annealing temperature is less than 550° C., and thesubstrate may be bent when it is more than 750° C.

Further, it is preferable that the pressure of H₂O is in the range of10,000 Pa to 2 MPa. A crystallization rate is proportional to thepressure and thus when the pressure is too low, the crystallization ratebecomes low and the annealing time becomes longer, affecting thesubstrate. On the other hand, too high pressure may cause explosion. Forthese reasons, the pressure of 10,000 Pa to 2 MPa is desirable forannealing.

Meanwhile, it is preferable to deposit the silicon layer to a thicknessof less than 2,000. Small thickness facilitates crystallization.However, too small thickness may affect the device characteristics whenthe polycrystalline silicon is used to form a thin film transistor.Accordingly, it is more preferable to deposit the silicon layer to athickness of 300 to 1,000.

As shown in FIG. 1C, a gate insulating layer 14 is formed of SiO₂ orSiNx on the semiconductor layer 12 a. A gate electrode 16 is formedcorresponding to an active channel region 100 c of the semiconductorlayer 12 a, as shown in FIG. 1D.

Ions are doped into the semiconductor layer 12 a using the gateelectrode 16 as a mask to form source and drain regions 100 a ad 100 b.The semiconductor layer 12 a, doped with the ions, is activated by anexcimer laser annealing (ELA) process, an RTA process or an annealingprocess in a furnace, preferably the RTA or annealing process in thefurnace, as shown in FIG. 1E.

Subsequently, an interlayer insulating layer, such as SiO₂ or SiNx, isformed on the gate electrode 16 over the entire surface of thesubstrate. The interlayer insulating layer is then patterned to exposethe source and drain regions 100 a and 100 b and source and drainelectrodes are formed, thus completing a semiconductor device.

FIGS. 2A to 2E sequentially illustrate a method of fabricating asemiconductor device according to a second embodiment of the presentinvention. The second embodiment of the present invention will bedescribed with reference to FIGS. 2A to 2E.

Referring to FIG. 2A, amorphous silicon, or a silicon layer 22containing a great quantity of amorphous silicon is deposited on asubstrate 20. At this time, a normally used insulating and transparentglass substrate is used as the substrate 20.

A typical deposition method, such as a plasma enhanced chemical vapordeposition (PECVD) method or a low-pressure chemical vapor deposition(LPCVD) method, is used to deposit the silicon layer. The PECVD methodis performed using SiH₄+Ar and/or H₂ under a pressure of 1 to 1.5 Torrat a temperature of 330 to 430° C. Further, the LPCVD method isperformed using Si₂H₆+Ar under a pressure of 0.2 to 0.4 Torr at atemperature of about 400 to 500° C.

Further, a buffer layer such as SiNx or SiO₂ may be further formed onthe substrate prior to depositing the amorphous silicon layer, in orderto prevent contaminants or the like created in the substrate fromdiffusing into the silicon layer or enhance interface characteristicsbetween the silicon layer and the substrate.

Photoresist is then coated on a channel region 200 c in the siliconlayer 22, not regions that will correspond to source and drain regions200 a and 200 b later, and impurity ions are implanted into the siliconlayer 22.

The photoresist is removed by, for example, photolithography and etchingprocesses and then the silicon layer 22 doped with the impurity ispatterned, as shown in FIG. 2B.

A gate insulating layer 24 is then formed of an inorganic insulatinglayer such as SiO₂ or SiNx on the patterned silicon layer 22, as shownin FIG. 2C.

Subsequently, as shown in FIG. 2D, a gate 26 is formed in a regioncorresponding to the channel region 200 c and annealing is carried out.

During the annealing process, the impurity ions doped into the sourceand drain regions 200 a and 200 b are activated and concurrently thesilicon layer 22 containing the amorphous silicon is crystallized intothe polycrystalline silicon layer 22 a.

In the present invention, a typical high-temperature annealing processsuch as a rapid thermal annealing (RTA) process is used as the annealingprocess. Conventional annealing is carried out under an inert N₂ or O₂atmosphere while the annealing in the present invention is carried outin an H₂O atmosphere.

The annealing in the H₂O atmosphere shortens annealing time under acondition of the same temperature and reduces annealing temperatureunder a condition of the same time, compared to the annealing in the N₂or O₂ atmosphere.

In particular, a conventional glass substrate that is a transparentinsulting substrate is bent due to a high temperature while thesubstrate in the present invention is not bent because the annealingtemperature may be lowered.

In the present invention, the annealing temperature is preferably in therange of 550 to 750° C. More preferably, the annealing temperature is inthe range of 600 to 710° C. because excellent polycrystalline siliconmay be achieved with a proper annealing time. Crystallization may not beachieved when the annealing temperature is less than 550° C., and thesubstrate may be bent when it is more than 750° C.

Further, it is preferable that the pressure of H₂O is in the range of10,000 Pa to 2 MPa. A crystallization rate is proportional to thepressure and thus when the pressure is too low, the crystallization ratebecomes low and the annealing time becomes longer, affecting thesubstrate. On the other hand, too high pressure may cause explosion. Forthese reasons, the pressure of 10,000 Pa to 2 MPa is desirable forannealing.

Meanwhile, it is preferable to deposit the silicon layer 22 to athickness of less than 2,000. Small thickness facilitatescrystallization. However, too small thickness may affect the devicecharacteristics when the polycrystalline silicon is used to form a thinfilm transistor. Accordingly, it is more preferable to deposit thesilicon layer to a thickness of 300 to 1,000.

Although the above-described processes suffice to obtain thepolycrystalline silicon, the present invention may further include anannealing process to reduce defects in the formed polycrystallinesilicon.

The further annealing process may be performed by an excimer laserannealing process or heating in a furnace.

Subsequently, as shown in FIG. 2E, an interlayer insulating layer 28 isformed on the gate electrode 26 over the entire surface of thesubstrate, and both the interlayer insulating layer 28 and the gateinsulating layer 24 are etched to form contact holes so that the sourceand drain regions 200 a and 200 b are open. Metal is filled into thecontact holes to form source and drain electrodes 29 a and 29 b, thuscompleting the thin film transistor.

FIGS. 3A to 3D sequentially illustrate a method of fabricating asemiconductor device according to a third embodiment of the presentinvention. The method of fabricating the semiconductor device accordingto the third embodiment of the present invention will be described withreference to FIGS. 3A to 3D.

Referring to FIG. 3A, patterning is carried out to form a gate electrode36 on a substrate 30. At this time, a normally used insulating andtransparent glass substrate is used as the substrate 30.

Further, a buffer layer such as SiNx or SiO₂ may be formed on thesubstrate 30 in order to prevent contaminants or the like created in thesubstrate from diffusing into the electrode or enhance interfacecharacteristics between the substrate and the electrode.

A gate insulating layer 34 is then formed of an inorganic insulatinglayer such as SiO₂ or SiNx on the gate electrode 36 over the entiresurface of the substrate 30.

Subsequently, amorphous silicon, or a silicon layer 32 containing agreat quantity of amorphous silicon is deposited on the gate insulatinglayer 34, as shown in FIG. 3B.

A typical deposition method, such as a plasma enhanced chemical vapordeposition (PECVD) method or a low-pressure chemical vapor deposition(LPCVD) method, is used to deposit the silicon layer 32. The PECVDmethod is performed using SiH₄+Ar and/or H₂ under a pressure of 1 to 1.5Torr at a temperature of 330 to 430° C. Further, the LPCVD method isperformed using Si₂H₆+Ar under a pressure of 0.2 to 0.4 Torr at atemperature of about 400 to 500° C.

Photoresist is then coated on a channel region 300 c in the siliconlayer 32, not regions that will correspond to source and drain regions300 a and 300 b later, and impurity ions are implanted into the siliconlayer 32, as shown in FIG. 3C.

Subsequently, annealing is carried out. During the annealing process,the impurity ions doped into the source and drain regions 300 a and 300b are activated and concurrently the silicon layer 32 containing theamorphous silicon is crystallized into the polycrystalline silicon layer32 a.

In the present invention, a typical high-temperature annealing processsuch as a rapid thermal annealing (RTA) process is used as the annealingprocess. Conventional annealing is carried out under an inert N₂ or O₂atmosphere while the annealing in the present invention is carried outin an H₂O atmosphere.

The annealing in the H₂O atmosphere shortens annealing time under acondition of the same temperature and reduces annealing temperatureunder a condition of the same time, compared to the annealing in the N₂or O₂ atmosphere.

In particular, a conventional glass substrate that is a transparentinsulting substrate is bent due to a high temperature while thesubstrate according to the present invention is not bent because theannealing temperature may be lowered.

In the present invention, the annealing temperature is preferably in therange of 550 to 750° C. More preferably, the annealing temperature is inthe range of 600 to 710° C. because excellent polycrystalline siliconmay be achieved with a proper annealing time. Crystallization may not beachieved when the annealing temperature is less than 550° C., and thesubstrate may be bent when it is more than 750° C.

Further, it is preferable that the pressure of H₂O is in the range of10,000 Pa to 2 MPa. A crystallization rate is proportional to thepressure and thus when the pressure is too low, the crystallization ratebecomes low and the annealing time becomes longer, affecting thesubstrate. On the other hand, too high pressure may cause explosion. Forthese reasons, the pressure of 10,000 Pa to 2 MPa is desirable forannealing.

Meanwhile, it is preferable to deposit the silicon layer 32 to athickness of less than 2,000. Small thickness facilitatescrystallization. However, too small thickness may affect the devicecharacteristics when the polycrystalline silicon is used to form a thinfilm transistor. Accordingly, it is more preferable to deposit thesilicon layer to a thickness of 300 to 1,000.

Although the above-described processes suffice to obtain thepolycrystalline silicon, the present invention may further include anannealing process to reduce defects in the formed polycrystallinesilicon.

The further annealing process may be performed by an excimer laserannealing process or heating in the furnace.

Subsequently, as shown in FIG. 3D, metal is deposited and patterned onthe polycrystalline silicon layer 32 a over the entire surface of thesubstrate to form source and drain electrodes 39 a and 39 b, therebyfabricating a semiconductor device.

In the present invention, it is desirable that the semiconductor deviceis a thin film transistor. The thin film transistor may be either a topgate thin film transistor in which the gate electrode 36 is formed onthe polycrystalline silicon layer 32 a, or a bottom gate thin filmtransistor in which the gate electrode 36 is formed under thepolycrystalline silicon layer 32 a.

Hereinafter, exemplary examples of the present invention are suggested.However, the examples described below are only intended to assist inunderstanding the present invention and not limit to the presentinvention.

EXAMPLES 1 to 3

An amorphous silicon layer was deposited to a thickness of 500 on asubstrate. As the deposition method, a low pressure chemical vapordeposition (LPCVD) method was used in Example 1, a plasma enhancedchemical vapor deposition (PECVD) method containing 2% or less ofhydrogen was used in Example 2, and a plasma enhanced chemical vapordeposition (PECVD) method containing 10% or more of hydrogen was used inExample 3. The amorphous silicon layer was annealed and crystallizedusing a rapid thermal annealing (RTA) process at about 710° C. for lessthan 10 minutes. The annealing was performed using an O₂ or N₂ carriergas in an H₂O atmosphere. Raman spectrum of the formed polycrystallinesilicon is shown in FIG. 4.

Referring to FIG. 4, it may be seen that the polycrystalline siliconobtained by annealing the amorphous silicon according to Examples 1 to 3of the present invention has excellent crystallinity because full widthat half maximum (FWHM) of a Raman peak is in the range of 4.5 to 7.5cm⁻¹. Considering that polycrystalline silicon fabricated by a typicalmethod has the Raman peak of more than 8.0 cm⁻¹, it may be seen that thecrystallinity in the present invention becomes excellent by depositingthe amorphous silicon using a low pressure chemical vapor deposition(LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD)method and then crystallizing the deposited amorphous silicon by an RTAprocess in an H₂O atmosphere.

The fabricated polycrystalline silicon thin film is applicable to a thinfilm transistor, and in turn the thin film transistor may be utilized ina flat panel display device, such as an organic light emitting displaydevice or a liquid crystal display device.

As described above, according to the present invention, it is possibleto reduce the annealing time and the annealing temperature by utilizingthe H₂O annealing atmosphere when the amorphous silicon is depositedusing the LPCVD or PECVD method and crystallized using the solid phasecrystallization method, thereby preventing process defects such as abent substrate and improving the crystallinity of the polycrystallinesilicon.

Although the present invention has been described with reference tocertain exemplary embodiments thereof, it will be understood by thoseskilled in the art that a variety of modifications and variations may bemade to the present invention without departing from the spirit or scopeof the present invention defined in the appended claims, and theirequivalents.

1. A method of fabricating a semiconductor device, comprising:depositing a silicon layer containing amorphous silicon on a substrateusing a plasma enhanced chemical vapor deposition (PECVD) method or alow pressure chemical vapor deposition (LPCVD) method; annealing thesilicon layer in an H₂O atmosphere at a predetermined temperature toform a polycrystalline silicon layer; forming a gate insulating layer onthe polycrystalline silicon layer; forming impurity regions in thepolycrystalline silicon layer to define source and drain regions; andactivating the impurity regions.
 2. The method according to claim 1,wherein the certain temperature is in a range of 550 to 750° C.
 3. Themethod according to claim 2, wherein the temperature is in a range of600 to 710° C.
 4. The method according to claim 1, wherein the H₂Opressure is in a range of 10,000 Pa to 2 MPa.
 5. The method according toclaim 1, wherein the silicon layer has a thickness of less than 2,000.6. The method according to claim 5, wherein the silicon layer has athickness of 300 to 1,000.
 7. The method according to claim 1, whereinactivating the impurity regions comprises crystallizing non-crystallizedamorphous silicon in the polycrystalline silicon layer and at the sametime activating the impurity regions by irradiating the impurity regionswith a laser.
 8. The method according to claim 1, wherein the PECVDmethod is performed using SiH₄+Ar and/or H₂ under a pressure of 1 to 1.5Torr at a temperature of 330 to 430° C., and the LPCVD method isperformed using Si₂H₆+Ar under a pressure of 0.2 to 0.4 Torr at atemperature of 400 to 500° C.
 9. A method of fabricating a semiconductordevice, comprising: depositing a silicon layer containing amorphoussilicon on a substrate using a plasma enhanced chemical vapor deposition(PECVD) method or a low pressure chemical vapor deposition (LPCVD)method; doping the silicon layer with impurity ions to define source anddrain regions; patterning the amorphous silicon to form a semiconductorlayer; forming a gate insulating layer on the semiconductor layer overan entire surface of the substrate; forming a gate electrode on the gateinsulating layer, the gate electrode corresponding to a channel regionof the semiconductor layer; and annealing the amorphous silicon in anH₂O atmosphere at a certain temperature to crystallize the amorphoussilicon and activate the impurity ions.
 10. The method according toclaim 9, wherein the temperature is in a range of 550 to 750° C.
 11. Themethod according to claim 10, wherein the temperature is in a range of600 to 710° C.
 12. The method according to claim 9, wherein the H₂Opressure is in a range of 10,000 Pa to 2 MPa.
 13. The method accordingto claim 9, wherein the silicon layer has a thickness of less than2,000.
 14. The method according to claim 13, wherein the silicon layerhas a thickness of 300 to 1,000.
 15. The method according to claim 9,wherein the PECVD method is performed using SiH₄+Ar and/or H₂ under apressure of 1 to 1.5 Torr at a temperature of 330 to 430° C., and theLPCVD method is performed using Si₂H₆+Ar under a pressure of 0.2 to 0.4Torr at a temperature of 400 to 500° C.
 16. A method of fabricating asemiconductor device, comprising: forming a gate electrode on asubstrate; forming a gate insulating layer on the gate electrode over anentire surface of the substrate; depositing a silicon layer containingamorphous silicon on the gate insulating layer using a plasma enhancedchemical vapor deposition (PECVD) method or a low pressure chemicalvapor deposition (LPCVD) method; doping impurity ions into the siliconlayer using photoresist to define source and drain regions; removing thephotoresist and then annealing the amorphous silicon in an H₂Oatmosphere at a certain temperature to crystallize the amorphous siliconand to activate the impurity ions; and patterning the gate insulatinglayer to form source and drain electrodes in the source and drainregions.
 17. The method according to claim 16, wherein the temperatureis in a range of 550 to 750° C.
 18. The method according to claim 17,wherein the temperature is in a range of 600 to 710° C.
 19. The methodaccording to claim 16, wherein the H₂O pressure is in a range of 10,000Pa to 2 MPa.
 20. The method according to claim 16, wherein the siliconlayer has a thickness of less than 2,000.
 21. The method according toclaim 20, wherein the silicon layer has a thickness of 300 to 1,000. 22.The method according to claim 16, wherein the PECVD method is performedusing SiH₄+Ar and/or H₂ under a pressure of 1 to 1.5 Torr at atemperature of 330 to 430° C., and the LPCVD method is performed usingSi₂H₆+Ar under a pressure of 0.2 to 0.4 Torr at a temperature of 400 to500° C.
 23. A semiconductor device fabricated by the method according toclaim 1, wherein the semiconductor device is a thin film transistor. 24.The device according to claim 23, wherein a polycrystalline silicon thinfilm constituting a semiconductor layer of the thin film transistor hasfull width at half maximum (FWHM) in a range of 4.5 to 7.5 cm⁻¹.
 25. Thedevice according to claim 23, wherein the thin film transistor is usedin at least one of an organic light emitting display device and a liquidcrystal display device.